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Espressif Systems /ESP32 /UHCI0 /CONF0

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Interpret as CONF0

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (IN_RST)IN_RST 0 (OUT_RST)OUT_RST 0 (AHBM_FIFO_RST)AHBM_FIFO_RST 0 (AHBM_RST)AHBM_RST 0 (IN_LOOP_TEST)IN_LOOP_TEST 0 (OUT_LOOP_TEST)OUT_LOOP_TEST 0 (OUT_AUTO_WRBACK)OUT_AUTO_WRBACK 0 (OUT_NO_RESTART_CLR)OUT_NO_RESTART_CLR 0 (OUT_EOF_MODE)OUT_EOF_MODE 0 (UART0_CE)UART0_CE 0 (UART1_CE)UART1_CE 0 (UART2_CE)UART2_CE 0 (OUTDSCR_BURST_EN)OUTDSCR_BURST_EN 0 (INDSCR_BURST_EN)INDSCR_BURST_EN 0 (OUT_DATA_BURST_EN)OUT_DATA_BURST_EN 0 (MEM_TRANS_EN)MEM_TRANS_EN 0 (SEPER_EN)SEPER_EN 0 (HEAD_EN)HEAD_EN 0 (CRC_REC_EN)CRC_REC_EN 0 (UART_IDLE_EOF_EN)UART_IDLE_EOF_EN 0 (LEN_EOF_EN)LEN_EOF_EN 0 (ENCODE_CRC_EN)ENCODE_CRC_EN 0 (CLK_EN)CLK_EN 0 (UART_RX_BRK_EOF_EN)UART_RX_BRK_EOF_EN

Fields

IN_RST

Set this bit to reset in link operations.
OUT_RST

Set this bit to reset out link operations.
AHBM_FIFO_RST

Set this bit to reset dma ahb fifo.
AHBM_RST

Set this bit to reset dma ahb interface.
IN_LOOP_TEST

Set this bit to enable loop test for in links.
OUT_LOOP_TEST

Set this bit to enable loop test for out links.
OUT_AUTO_WRBACK

when in link’s length is 0 go on to use the next in link automatically.
OUT_NO_RESTART_CLR

don’t use
OUT_EOF_MODE

Set this bit to produce eof after DMA pops all data clear this bit to produce eof after DMA pushes all data
UART0_CE

Set this bit to use UART to transmit or receive data.
UART1_CE

Set this bit to use UART1 to transmit or receive data.
UART2_CE

Set this bit to use UART2 to transmit or receive data.
OUTDSCR_BURST_EN

Set this bit to enable DMA in links to use burst mode.
INDSCR_BURST_EN

Set this bit to enable DMA out links to use burst mode.
OUT_DATA_BURST_EN

Set this bit to enable DMA burst MODE
MEM_TRANS_EN
SEPER_EN

Set this bit to use special char to separate the data frame.
HEAD_EN

Set this bit to enable to use head packet before the data frame.
CRC_REC_EN

Set this bit to enable receiver’'s ability of crc calculation when crc_en bit in head packet is 1 then there will be crc bytes after data_frame
UART_IDLE_EOF_EN

Set this bit to enable to use idle time when the idle time after data frame is satisfied this means the end of a data frame.
LEN_EOF_EN

Set this bit to enable to use packet_len in packet head when the received data is equal to packet_len this means the end of a data frame.
ENCODE_CRC_EN

Set this bit to enable crc calculation for data frame when bit6 in the head packet is 1.
CLK_EN

Set this bit to enable clock-gating for read or write registers.
UART_RX_BRK_EOF_EN

Set this bit to enable to use brk char as the end of a data frame.

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data